A representative example of a conventional technology concerning a bus and its controlling method used in the information processing apparatus, such as a personal computer or a workstation, is shown in JP-A-5-324544. This conventional method of controlling the bus will be explained below, using FIG. 8. At present, due to the ease with which the interface circuit can be designed, a synchronous-type bus has become the mainstream device for such use. With respect to such a synchronous-type bus, a plurality of modules connected to the synchronous-type bus execute transmitting/receiving control of data in synchronization with a system clock, i.e., a clock that is common to the respective modules.
Taking as an example a burst write operation with a 4-data cycle and explaining the transferring system of the conventional synchronous-type bus, the explanation can be illustrated in FIG. 8. FIG. 8 is a burst write timing chart of a conventional bus arrangement(in which the transfer destination module-side buffer is in an empty state). In FIG. 8, the reference numerals denote the following signals, respectively: 801 a system clock signal with which a transfer should be performed in synchronization, 802 an address/data (A/D) signal for transmitting address/data from a transfer source module (bus master) to the transfer destination module (slave) through a bus module, 803 an address-valid (ADV-N) signal for indicating a valid time-period of an address/command, 804 a data-valid (DTV-N) signal for indicating a valid time-period of the data, 805 a command (CMD) signal for specifying information such as the type of the transfer, 806 an acknowledge (ACK-N) signal with which the bus module acknowledges the transfer source module (bus master) that the bus module has accepted the transfer, 807 a retry requesting (RTY-N) signal with which the transfer destination module (slave) requests the transfer source module (bus master) to execute the transfer once again at a later time since a buffer within the transfer destination module has been fully occupied and is now in a state of being unable to accept the transfer.
The bus master, i.e., the transfer source, sends out the transfer address and the transfer command onto the bus in synchronism with the system clock 801. At this time, by asserting the address-valid signal 803, the bus master specifies that the transfer is an address/command cycle. Next, through the acknowledge signal clock 806, the slave module, i.e., the transfer destination, informs the bus master of a report that the slave module has actually received the address/command cycle. Having received the report, the bus master sends out data onto the bus, utilizing continuous 4-data cycles in synchronism with the system 801, thereby terminating the data transfer. At this time, by using the data-valid signal 804, the bus master specifies that the transfer is a data cycle.
Meanwhile, in recent years, the integration scale of LSI devices has been steadily increasing. As a result, it is now becoming possible to integrate, all together on a single chip, a plurality of functions constituting the system, such as a processor, a memory and various types of peripheral function modules. In this case, it can be considered that the above-described bus should be installed inside the LSI as an on-chip bus. Some advantages of providing the bus inside the LSI are that it is possible to make the interface circuit common to the respective modules, it is possible to make it easier to divert and employ the various types of function modules into the other LSIs, and so on.
U.S. Pat. No. 5,761,516 has disclosed a conventional example in which a bus has been installed inside an LSI as a on-chip bus.
In general, in a system where a bus such as described above is used, a buffer which is fully occupied within the transfer destination module causes a waiting state on the bus. This results in a problem that the system performance will be deteriorated. FIG. 9 provides an illustration of such a waiting state with a burst write over 4 data cycles, as an example.
FIG. 9 is a timing chart for a burst write operation on a conventional bus (in which the transfer destination module-side buffer is in a full state). In FIG. 9, the reference numerals denote the following signals, respectively: 901 a system clock signal with which a transfer should be performed in synchronization, 902 an address/data (A/D) signal for transmitting address/data from a transfer source module (bus master) to the transfer destination module (slave) through a bus module, 903 an address-valid (ADV-N) signal for indicating a valid time-period of an address/command, 904 a data-valid (DTV-N) signal for indicating a valid time-period of the data, 905 a command (CMD) signal for specifying information such as the type of the transfer, 906 an acknowledge (ACK-N) signal with which the bus module acknowledges to the transfer source module (bus master) that the bus module has accepted the transfer, and 907 a retry requesting (RTY-N) signal with which the transfer destination module (slave) requests the transfer source module (bus master) to execute the transfer once again at a later time since a buffer within the transfer destination module has been fully occupied and is now in a state of being unable to accept the transfer. The bus master, i.e., the transfer source, sends out a transfer address and a transfer command onto the bus in synchronism with the system clock 901. At this time, by asserting the address-valid signal 903, the bus master specifies that the transfer is an address/command cycle.
Here, when the buffer within the slave module, that is, the transfer destination, has been fully occupied and is in the state of being unable to receive anymore data, the slave module, using the retry requesting (RTY-N) signal 907, requests the bus master to execute the transfer once again at a later time. After the lapse of a fixed time interval, the bus master starts the transfer on the bus again. At this time, if the buffer within the slave module, that is, the transfer destination, has not been fully occupied, after receiving a report of the transfer acknowledgement from the slave module (that is, no retry request is received), the bus master executes a transfer of a burst write operation over 4 data cycles, thereby terminating the data transfer. In this case, the bus is equipped with a retry protocol, and, accordingly, the bus master is not kept waiting while occupying the bus, thus causing no disturbance to the other transfers. During at least the above-described fixed time interval, however, the transfer destination module never accepts the data transfer from the transfer source module that has already received the retry request. Consequently, there still remains the problem that the transfer source module is incapable of proceeding to the subsequent process.
In an LSI system where the on-chip bus is employed, depending on the buffer state in the transfer destination module, the bus transfer is kept waiting. This results in a situation that it becomes impossible for the transfer source module to proceed to the next process for the bus transfer. An object of the present invention is to prevent this situation.